1. Field
Embodiments of the present invention generally relate to control of single instruction multiple data (SIMD) units in graphics processing units (GPUs).
2. Background Art
A math unit of a graphics processor includes arithmetic logical units (ALUs) or math units configured to perform integer, logical and single/double precision floating point operations.
Graphics processors can include an array of such math units, known as a shader core. A shader core includes a shader pipeline (SP). To achieve higher performance, multiple SPs can be configured to work together as stacked SPs. SPs can be structured as an array of quad pipes (QPs) and SIMDs. All shader units of each SIMD can conditionally execute an identical ALU instruction on different sets of primitive, vertex, or pixel values. In this way, SIMDs provide mathematical processing power to a graphics processor.
In conventional graphics processors having stacked SPs, SIMDs can be enabled or disabled statically. For example, if a SP was determined to be faulty, a fuse mask can be programmed to disable the faulty SP. Similarly a user accessible register can be programmed to disable/enable a specific SIMD or group of SIMDs. However, such methods require flushing of a graphics pipe of the graphics processor and reprogramming of new values into the flushed graphics pipe before sending new work requests to the SIMDs.
Furthermore, in conventional approaches, clocking of all SIMD units in a shader complex is either enabled or disabled simultaneously. In many applications, not all SIMDs are assigned work. However, conventional approaches continue to actively provide clocking signals to such SIMDs. This approach can increase power consumption of a graphics processor and is inefficient.
Accordingly, systems and methods are needed that enable dynamic control of SIMDs and reduce power consumption of a graphics processor when SIMDs may not be performing processing tasks.